1. Field of the Invention
This invention generally relates to semiconductor manufacturing equipment and, more particularly, to a system and method used for rapid thermal processing of a semiconductor wafer.
2. Description of Related Art
In the semiconductor industry, to allow advancements in the development of semiconductor devices, especially semiconductor devices of decreased dimensions, new processing and manufacturing techniques have been developed. One such processing technique is known as Rapid Thermal Processing (RTP), which reduces the amount of time that a semiconductor device is exposed to high temperatures during processing. The rapid thermal processing technique, typically includes raising the temperature of the semiconductor device and holding the device at that temperature for a time long enough to successfully perform a fabrication process, to avoid unwanted dopant diffusion that would otherwise occur at the high processing temperatures.
Unfortunately, wafers which undergo RTP are extremely susceptible to forming defects, such as slip dislocations. Slip generally occurs when transient temperature fluctuations occur during processing at high temperatures (e.g. xcx9c1000xc2x0 C.). Slip dislocations may also be formed due to thermal or mechanical shock. For example, when the wafer is above a critical temperature for the formation of slip dislocations, contact from a removal device can cause the wafer to be cooled down in a non-uniform manner and/or to be subject to unwanted vibration.
For the above reasons, a system and method are needed for removing a heated wafer from a processing chamber without causing the formation of slip dislocations.
The present invention provides a system and method for providing substantially defect free rapid thermal processing. The present invention includes a wafer processing system used to process semiconductor wafers into electronic devices. Typically, a carrier containing wafers is loaded into a loading station and transferred to a load lock. Subsequently, a robot picks up a wafer from the carrier and moves the wafer into a reactor (also known as a process chamber). The wafer is processed in the reactor according to well-known wafer processing techniques. In accordance with the present invention, once the wafer is processed, a shield can be inserted into the reactor to a position between the reactor heating surface and the wafer. Once inserted, the shield blocks radiated heat energy from directly impinging on the wafer surface, which causes the temperature of the wafer to be reduced. In a dual heating surface reactor, a second shield may be inserted between the wafer and the second heating surface. Once the temperature of the wafer is reduced to below a predetermined critical temperature, the robot picks up the wafer and removes the wafer from the processing chamber.
In one aspect of the present invention, a semiconductor wafer processing system is provided. The system includes a process chamber, which defines a cavity configured to receive a wafer. The system also includes a robot. The robot is operable to move a wafer to and/or from the process chamber. A shield mechanism is provided which is operable to block the wafer from a heating source.
In another aspect of the present invention, a method is provided for processing a semiconductor wafer. The method includes inserting a shield mechanism into a wafer processing chamber proximate to a processed wafer; where the shield mechanism causes a temperature of the wafer to be reduced.
One advantage of using the shield of the present invention is to cause the temperature of the wafer to be reduced to below a critical slip dislocation formation temperature, by blocking direct radiation heating. Since the temperature is below the critical slip formation temperature, the robot can pick up the wafer without causing thermal and mechanical shock to the wafer, without having to heat the arm or end-effector of the robot. The heat shields also remove the need to lower the temperature of the reactor between each wafer being processed. Accordingly, processing times and system costs are reduced, while wafer defects are minimized.